Design of robust electrostatic discharge (ESD) protection is important for integrated circuits in, for example, both wire-bond and flip-chip packages. In an effort to protect the I/O cells in the I/O ring around the perimeter of an integrated circuit (IC) device, a designer often places ESD diodes between each I/O pad and the local I/O power (VDD) and ground (VSS) buses. In addition, active rail clamp circuits, comprising a transient detector circuit and a metal-oxide field-effect transistor (MOSFET) clamp, often are placed to provide ESD protection between the VDD and VSS buses. These clamp transistors, also referred to as “ESD clamp transistors”, “clamp transistors,” or simply “clamps,” typically are distributed in parallel in power cells, ground cells, I/O cells or spacer cells in the I/O ring of the integrated circuit. The clamp transistors collectively form an ESD clamp transistor network. In some IC designs there are very few or no power/ground cells or spacer cells placed in the I/O ring. For example, in an IC designed for flip-chip packaging, off-chip connections to the VDD and VSS buses are typically made via bumps, without need for any power or ground cells in the I/O ring. Spacer cells require additional space in the I/O ring which is unfavorable, especially for designs with a large number of I/O cells. The implication for the ESD designer is that all ESD protection circuitry, including ESD clamp transistors, should ideally be contained within the I/O cells themselves. These ESD protection networks typically employ I/O cells with clamp transistors having the same relatively large channel width. This arrangement typically results in overprotection for the I/O cells on the interior of the I/O cell bank and underprotection for the I/O cells at the edges of the I/O cell bank, as well as excess current leakage by the ESD clamps. Accordingly, an improved ESD protection technique would be advantageous.
The use of the same reference symbols in different drawings indicates similar or identical items.